A Study of SCEs and Analog FOMs in GS-DG- MOSFET with Lateral Asymmetric Channel Doping

The design and analysis of analog circuit application on CMOS technology are a challenge in deep sub-micrometer process. This paper is a study on the performance value of Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with Gate Stack and the channel engineering Single Halo (SH), Double Halo (DH). Four different structures have been analysed keeping channel length constant. The short channel parameters and different sub-threshold analog figures of merit (FOMs) are analysed. This work extensively provides the device structures which may be applicable for high speed switching and low power consumption application.

[1]  Denis Flandre,et al.  Influence of device engineering on the analog and RF performances of SOI MOSFETs , 2003 .

[2]  Jeffrey Bokor,et al.  Extremely scaled silicon nano-CMOS devices , 2003, Proc. IEEE.

[3]  Zhiping Yu,et al.  Design considerations of high-/spl kappa/ gate dielectrics for sub-0.1-/spl mu/m MOSFET's , 1999 .

[4]  H.-S. Philip Wong Beyond the conventional transistor , 2002, IBM J. Res. Dev..

[5]  Yuan Taur,et al.  Device scaling limits of Si MOSFETs and their application dependencies , 2001, Proc. IEEE.

[6]  Jean-Pierre Colinge,et al.  Multiple-gate SOI MOSFETs , 2004 .

[7]  C. Hu,et al.  A comparative study of advanced MOSFET concepts , 1996 .

[8]  S. Mahapatra,et al.  Modeling of Channel Potential and Subthreshold Slope of Symmetric Double-Gate Transistor , 2009, IEEE Transactions on Electron Devices.

[9]  S. M. Sze,et al.  Physics of semiconductor devices , 1969 .

[10]  V. Ramgopal Rao,et al.  Optimization and realization of sub-100-nm channel length single halo p-MOSFETs , 2002 .

[11]  Abhinav Kranti,et al.  Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications , 2004 .

[12]  Mamidala Jagadesh Kumar,et al.  Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study , 2004, Microelectron. J..

[13]  Y. Tosaka,et al.  Scaling theory for double-gate SOI MOSFET's , 1993 .

[14]  R. Pierret,et al.  Dual-gate operation and volume inversion in n-channel SOI MOSFET's , 1992, IEEE Electron Device Letters.

[15]  Jason C. S. Woo,et al.  Gate Stack Architecture Analysis and Channel Engineering in Deep Sub-Micron MOSFETs , 1999 .

[16]  Sorin Cristoloveanu,et al.  Frontiers of silicon-on-insulator , 2003 .

[17]  S. Thompson MOS Scaling: Transistor Challenges for the 21st Century , 1998 .

[18]  T. Sugii,et al.  Scaling-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFET's , 1994, IEEE Electron Device Letters.

[19]  K. F. Lee,et al.  Scaling the Si MOSFET: from bulk to SOI to bulk , 1992 .

[20]  Zunchao Li,et al.  A Single-Halo Dual-Material Gate SOI MOSFET , 2007, 2007 International Workshop on Electron Devices and Semiconductor Technology (EDST).

[21]  Chenming Hu Gate oxide scaling limits and projection , 1996, International Electron Devices Meeting. Technical Digest.

[22]  M. J. Kumar,et al.  Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review , 2004, IEEE Transactions on Device and Materials Reliability.

[23]  C.K. Sarkar,et al.  Influence of Channel and Gate Engineering on the Analog and RF Performance of DG MOSFETs , 2010, IEEE Transactions on Electron Devices.

[24]  Bin Yu,et al.  Short-channel effect improved by lateral channel-engineering in deep-submicronmeter MOSFET's , 1997 .

[25]  S. Chakraborty,et al.  Impact of Halo Doping on the Subthreshold Performance of Deep-Submicrometer CMOS Devices and Circuits for Ultralow Power Analog/Mixed-Signal Applications , 2007, IEEE Transactions on Electron Devices.