Security Aspects of Neuromorphic MPSoCs
暂无分享,去创建一个
[1] Michael Hamburg,et al. Spectre Attacks: Exploiting Speculative Execution , 2018, 2019 IEEE Symposium on Security and Privacy (SP).
[2] Michael Hamburg,et al. Meltdown: Reading Kernel Memory from User Space , 2018, USENIX Security Symposium.
[3] Hong Wang,et al. Loihi: A Neuromorphic Manycore Processor with On-Chip Learning , 2018, IEEE Micro.
[4] Yoshua Bengio,et al. Gradient-based learning applied to document recognition , 1998, Proc. IEEE.
[5] Chip-Hong Chang,et al. Static and Dynamic Obfuscations of Scan Data Against Scan-Based Side-Channel Attacks , 2017, IEEE Transactions on Information Forensics and Security.
[6] Cezar Reinbrecht,et al. Earthquake — A NoC-based optimized differential cache-collision attack for MPSoCs , 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[7] Andreas Mayr,et al. CrossNets: High‐Performance Neuromorphic Architectures for CMOL Circuits , 2003, Annals of the New York Academy of Sciences.
[8] Liam McDaid,et al. A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network-On-Chip and Spiking Neural Networks , 2009, Int. J. Reconfigurable Comput..
[9] Cezar Reinbrecht,et al. DHyANA: A NoC-based neural network hardware architecture , 2016, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS).
[10] Tobi Delbruck,et al. Real-time classification and sensor fusion with a spiking deep belief network , 2013, Front. Neurosci..
[11] Carver A. Mead,et al. Neuromorphic electronic systems , 1990, Proc. IEEE.
[12] Cezar Reinbrecht,et al. Understanding MPSoCs: exploiting memory microarchitectural vulnerabilities of high performance NoC-based MPSoCs , 2018, SAMOS.
[13] M. Hofman,et al. Evolution of the primate brain : from neuron to behavior , 2012 .
[14] Wei Yang Lu,et al. Nanoscale memristor device as synapse in neuromorphic systems. , 2010, Nano letters.
[15] Jim D. Garside,et al. Overview of the SpiNNaker System Architecture , 2013, IEEE Transactions on Computers.
[16] Rodrigo Alvarez-Icaza,et al. Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations , 2014, Proceedings of the IEEE.
[17] Paul C. Kocher,et al. Differential Power Analysis , 1999, CRYPTO.
[18] Giacomo Indiveri,et al. A reconfigurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128K synapses , 2015, Front. Neurosci..
[19] David Naccache,et al. The Sorcerer's Apprentice Guide to Fault Attacks , 2006, Proceedings of the IEEE.
[20] Jean-Pierre Seifert,et al. Cloning Physically Unclonable Functions , 2013, 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).
[21] Matthew Cook,et al. Unsupervised learning of digit recognition using spike-timing-dependent plasticity , 2015, Front. Comput. Neurosci..
[22] D. Schmidt. Automated Characterization of a Wafer-Scale Neuromorphic Hardware System , 2014 .
[23] Ross J. Anderson,et al. On a new way to read data from memory , 2002, First International IEEE Security in Storage Workshop, 2002. Proceedings..
[24] Francis Olivier,et al. Electromagnetic Analysis: Concrete Results , 2001, CHES.
[25] Ramesh Karri,et al. Attacks and Defenses for JTAG , 2010, IEEE Design & Test of Computers.
[26] R. Jordan,et al. NVM neuromorphic core with 64k-cell (256-by-256) phase change memory synaptic array with on-chip neuron circuits for continuous in-situ learning , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).
[27] Martha Johanna Sepúlveda,et al. Scalable NoC-based architecture of neural coding for new efficient associative memories , 2013, 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).
[28] Cezar Reinbrecht,et al. Gossip NoC -- Avoiding Timing Side-Channel Attacks through Traffic Management , 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).
[29] Ricardo Augusto da Luz Reis,et al. Low Latency FPGA Implementation of Izhikevich-Neuron Model , 2015, IESS.