Mixed-mode simulation of compiled VHDL programs

The VHSIC hardware description language (VHDL) supports the hierarchical design, documentation, and simulation of a wide range of digital system abstractions. VHDL, however, is often cited as difficult to use and inefficient for simulating designs below the gate level. The authors present the mixed-mode simulation facilities of a VHDL system that overcome this limitation by effectively merging gate and switch primitive evaluation routines with VHDL processes. A high-performance mixed-mode simulation capability is achieved through integrated approaches to interface compilation, data structuring, and implementation of the simulation cycle. Several experimental results serve as preliminary justification for this methodology.<<ETX>>