A Framework for Area-Efficient Concurrent Online Checkers Design

This paper proposes a framework for automated evaluation and minimization of concurrent online checkers, with the aim of both achieving minimal fault detection latency, while at the same time maintaining the fault detection capabilities and keeping area consumption within the acceptable range. The proposed framework can be utilized for any digital circuit, however, our focus in this work as a case study is applying the framework to the control part of a Network-on-Chip router consisting of the routing computation and arbitration units. The novelty of the framework is its ability to formally prove the presence or absence of true misses. Experiments are performed both regarding the latency and the fault coverage of the checkers devised by the framework which indicate 100% fault coverage with acceptable area overhead and also instant (one cycle) detection of faults in the control part of a NoC router. Keywords— Network-on-Chip, routing logic, arbitration, concurrent online checking.

[1]  Jay M. Berger.  A Note on Error Detection Codes for Asymmetric Channels , 1961, Inf. Control..

[2]  Yiorgos Makris,et al.  Concurrent fault detection in random combinational logic , 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

[3]  R. Iris Bahar,et al.  Enhancing online error detection through area-efficient multi-site implications , 2011, 29th VLSI Test Symposium.

[4]  Armin Alaghi,et al.  Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Model , 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

[5]  Kewal K. Saluja,et al.  An implementation and analysis of a concurrent built-in self-test technique , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[6]  Chrysostomos Nicopoulos,et al.  NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures , 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

[7]  Valeria Bertacco,et al.  Formally enhanced runtime verification to ensure NoC functional correctness , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[8]  S. Katkoori,et al.  Selective triple Modular redundancy (STMR) based single-event upset (SEU) tolerant synthesis for FPGAs , 2004, IEEE Transactions on Nuclear Science.

[9]  Zeljko Zilic,et al.  Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[10]  Nur A. Touba,et al.  Synthesis of low power CED circuits based on parity codes , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[11]  José Duato,et al.  Logic-Based Distributed Routing for NoCs , 2008, IEEE Computer Architecture Letters.

[12]  R. Ubar,et al.  Structurally synthesized binary decision diagrams , 2004 .

[13]  Artur Jutman,et al.  Turbo Tester – diagnostic package for research and training , 2003 .

[14]  Paul Ampadu,et al.  Transient and Permanent Error Control for High-End Multiprocessor Systems-on-Chip , 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

[15]  Nur A. Touba,et al.  Synthesis of low-cost parity-based partially self-checking circuits , 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..