Nostradamus: a floorplanner of uncertain designs
暂无分享,去创建一个
[1] D. F. Wong,et al. Simulated Annealing for VLSI Design , 1988 .
[2] Ernest S. Kuh,et al. Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[3] Malgorzata Marek-Sadowska,et al. Floorplanning with pin assignment , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[4] Thomas Lengauer,et al. A robust framework for hierarchical floorplanning with integrated global wiring , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[5] Martin D. F. Wong,et al. Efficient Floorplan Area Optimization , 1989, 26th ACM/IEEE Design Automation Conference.
[6] Majid Sarrafzadeh,et al. An Introduction To VLSI Physical Design , 1996 .
[7] J. Ben Rosen,et al. An analytical approach to floorplan design and optimization , 1990, 27th ACM/IEEE Design Automation Conference.
[8] Ikuo Harada,et al. CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[9] Majid Sarrafzadeh. Transforming an arbitrary floorplan into a sliceable one , 1993, ICCAD.
[10] Carl Sechen,et al. IMPROVED SIMULATED ANNEALING ALGORIHM FOR ROW-BASED PLACEMENT. , 1987 .
[11] Majid Sarrafzadeh,et al. A unified approach to floorplan sizing and enumeration , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[12] Majid Sarrafzadeh,et al. Floor-Planning by Graph Dualization: 2-Concave Rectilinear Modules , 1993, SIAM J. Comput..
[13] Thomas Lengauer,et al. Combinatorial algorithms for integrated circuit layout , 1990, Applicable theory in computer science.
[14] Ting-Chi Wang,et al. An optimal algorithm for floorplan area optimization , 1990, 27th ACM/IEEE Design Automation Conference.
[15] P. A. Subrahmanyam,et al. A Note on Clustering Modules for Floorplanning , 1989, 26th ACM/IEEE Design Automation Conference.
[16] Naveed A. Sherwani,et al. Algorithms for VLSI Physical Design Automation , 1999, Springer US.
[17] Ting-Chi Wang,et al. A graph theoretic technique to speed up floorplan area optimization , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[18] Edwin Kinnen,et al. Rectangular duals of planar graphs , 1985, Networks.
[19] Sartaj Sahni,et al. A linear algorithm to find a rectangular dual of a planar triangulated graph , 1986, 23rd ACM/IEEE Design Automation Conference.
[20] Majid Sarrafzadeh,et al. Sliceable Floorplanning by Graph Dualization , 1995, SIAM J. Discret. Math..