Effects of microvia build-up layers on the solder joint reliability of a wafer level chip scale package (WLCSP)
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John H. Lau | J. Lau | S. Lee | S.-W.R. Lee
[1] J. Lau,et al. Creep Analysis of Wafer Level Chip Scale Package (WLCSP) With 96.5Sn-3.5Ag and 100In Lead-Free Solder Joints and Microvia Build-Up Printed Circuit Board , 2000, Packaging of Electronic and Photonic Devices.
[2] John H. Lau,et al. Chip scale package (CSP) : design, materials, processes, reliability, and applications , 1999 .
[3] J. Lau,et al. Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies , 1996 .
[4] P. Garrou,et al. Wafer level chip scale packaging (WL-CSP): an overview , 2000, ECTC 2000.
[5] John H. Lau,et al. An overview of microvia technology , 2000 .
[6] John H. Lau,et al. Solder joint crack propagation analysis of wafer-level chip scale package on printed circuit board assemblies , 2001 .
[7] D.C. O'Brien,et al. Fabrication of wafer level chip scale packaging for optoelectronic devices , 1999, 1999 Proceedings. 49th Electronic Components and Technology Conference (Cat. No.99CH36299).
[8] Thomas Oppert,et al. Wafer level CSP using low cost electroless redistribution layer , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).
[9] A.R. Mirza. One micron precision, wafer-level aligned bonding for interconnect, MEMS and packaging applications , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).
[10] John H. Lau,et al. Microvias: For Low Cost, High Density Interconnects , 2001 .
[11] H. Reichl,et al. Fab Integrated Packaging (FIP): a new concept for high reliability wafer-level chip size packaging , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).
[12] J. Lau,et al. Nonlinear-Time-Dependent Analysis of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications , 2000, Packaging of Electronic and Photonic Devices.
[13] Recent advances on a wafer-level flip chip packaging process , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).
[14] Sa-Yoon Kang,et al. Optimal structure of wafer level package for the electrical performance , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).
[15] J. Lau. Ball Grid Array Technology , 1994 .
[16] J. Lau,et al. Thermal Stress and Strain in Microelectronics Packaging , 1993 .
[17] J. H. Lau,et al. Solder Joint Reliability of Wafer Level Chip Scale Packages (WLCSP): A Time-Temperature-Dependent Creep Analysis , 2000 .
[18] J.H. Lau. Critical issues of wafer level chip scale package (WLCSP) with emphasis on cost analysis and solder joint reliability , 2000, Twenty Sixth IEEE/CPMT International Electronics Manufacturing Technology Symposium (Cat. No.00CH37146).
[19] N. Kelkar,et al. A manufacturing perspective of wafer level CSP , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).
[20] J. Lau,et al. Creep behaviors of flip chip on board with 96.5Sn-3.5Ag and 100In lead-free solder joints , 2000 .
[21] K. Banerji,et al. Constitutive relations for tin-based-solder joints , 1992, 1992 Proceedings 42nd Electronic Components & Technology Conference.
[22] John H. Lau,et al. A New Thermal-Fatigue Life Prediction Model for Wafer Level Chip Scale Package (WLCSP) Solder Joints , 2000, Packaging of Electronic and Photonic Devices.
[23] John H. Lau,et al. Nonlinear fracture mechanics analysis of wafer level chip scale package solder joints with cracks , 2000 .
[24] Herbert Reichl,et al. Board level reliability of a waferlevel CSP using stacked solder spheres and a solder support structure (S/sup 3/) , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).
[25] John H. Lau,et al. Elastic, elastic‐plastic and creep analyses of wafer level chip scale package solder joints on microvia build‐up printed circuit boards , 2001 .