Moment computations for R(L)C interconnects with multiple resistor loops using ROBDD techniques

A new moment computation technique for general lumped R(L)C interconnect circuits with multiple resistor loops is proposed. Using the concept of tearing, a lumped R(L)C network can be partitioned into a spanning tree and several resistor links. The contributions of network moments from each tree and the corresponding links can be determined independently. By combining the conventional moment computation algorithms and the reduced ordered binary decision diagram (ROBDD), the proposed method can compute system moments efficiently

[1]  Ernest S. Kuh,et al.  Exact moment matching model of transmission lines and application to interconnect delay estimation , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Keith A. Jenkins,et al.  When are transmission-line effects important for on-chip interconnections? , 1997 .

[3]  Wu-Shiung Feng,et al.  Applications of tree/link partitioning for moment computations of general lumped RLC networks with resistor loops , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[4]  Malgorzata Marek-Sadowska,et al.  Crosstalk in VLSI interconnections , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Lawrence T. Pileggi,et al.  RICE: rapid interconnect circuit evaluation using AWE , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  R. A. Rohrer.  Circuit partitioning simplified , 1988 .

[7]  Jeremy C. Wyatt.  Signal delay in rc mesh networks , 1985 .

[8]  Lawrence T. Pileggi,et al.  Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Mark Horowitz,et al.  Techniques for calculating currents and voltages in VLSI power supply networks , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Pak K. Chan,et al.  Computing signal delay in general RC networks by tree/link partitioning , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Roland W. Freund,et al.  Efficient linear circuit analysis by Pade´ approximation via the Lanczos process , 1994, EURO-DAC '94.