A low cost individual-well adaptive body bias (IWABB) scheme for leakage power reduction and performance enhancement in the presence of intra-die variations

This paper presents a new method of adapting body biasing on a chip during post-fabrication testing in order to mitigate the effects of process variations. Individual well biasing voltages can be changed to be connected either to a chip wide well bias or to a different bias voltage through a self-regulating mechanism, allowing biasing voltage adjustments on a per well basis. The scheme requires only one bias voltage distribution network, but allows for back biasing adjustments to more effectively mitigate die-to-die and within-die process variations. The biasing setting for each well is determined using a modified genetic algorithm. Our experimental results show that binning yields as low as 17% can be improved to greater than 90% after using the proposed IWABB method.

[1]  Masayuki Miyazaki,et al.  A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs , 1998, ISLPED '98.

[2]  Eric R. Ziegel,et al.  Applied Multivariate Data Analysis , 2002, Technometrics.

[3]  T. Kuroda A 0.9V 150MHz 10mW 4mm^2 2-D Discrete Cosine Transform Core Processor with Variable-Threshold-Voltage Scheme , 1996 .

[4]  D. Boning,et al.  Statistical metrology - measurement and modeling of variation for advanced process development and design rule generation , 1998 .

[5]  David Blaauw,et al.  Modeling and analysis of leakage power considering within-die process variations , 2002, ISLPED '02.

[6]  K. Ishibashi,et al.  A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSls , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[7]  Norman J. Rohrer,et al.  SOI circuit design concepts , 2000 .

[8]  W. C. Riordan,et al.  Microprocessor reliability performance as a function of die location for a 0.25 /spl mu/, five layer metal CMOS logic process , 1999, 1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296).

[9]  S. Nassif,et al.  Delay variability: sources, impacts and trends , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[10]  Jeffrey Bokor,et al.  Channel doping engineering of MOSFET with adaptable threshold voltage using body effect for low voltage and low power applications , 1995, 1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers.

[11]  J.D. Meindl,et al.  Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[12]  Tughrul Arslan,et al.  Proceedings Design, Automation and Test in Europe Conference and Exhibition , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[13]  Duane S. Boning,et al.  Statistical metrology: understanding spatial variation in semiconductor manufacturing , 1996, Advanced Lithography.

[14]  G. Ono,et al.  A 1000-MIPS/W microprocessor using speed adaptive threshold-voltage CMOS with forward bias , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[15]  Vivek De,et al.  Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).