High-Frequency and ETP-Efficient Range-Matching Scheme

A dynamic–static mixed range-matching scheme is proposed, which significantly increases system clock frequency and reduces $$\hbox {Energy-T}_{\mathrm {clock}}$$Energy-Tclock-Product (ETP). Furthermore, the range-matching cell adopted in the current scheme presents higher-speed performance although it uses two transistors less than the previous one. Using 1.2V SMIC 130 nm process, the proposed 16-bit range-matching word (RMW) can work in the minimal clock cycle of 0.753 ns. In case of 50 % duty cycle ratio and the minimal clock cycle, the ETP of proposed RMW is 5.947 fJ $$\cdot $$· ns/bit/search.