A 7-bit 40 MS/s single-ended asynchronous SAR ADC in 65 nm CMOS

This paper presents a 7-bit 40 MS/s single-ended asynchronous SAR ADC intended for in-probe use in medical applications, which requires small area and good power efficiency. A single-ended architecture is proposed for a moderate resolution for its simplicity. Together with a double reference technique, the architecture reduces the area of the technology-limited large capacitors. The speed is optimized by an asymmetric delay line embedded in the asynchronous digital logic, enabling a sampling frequency of 40 MS/s. The prototype is fabricated in a 65 nm CMOS technology. Measurement shows that at 1 V supply and 40 MS/s, the ADC achieves an SNDR of 39.73 dB and an ENOB of 6.3 bit, while consuming 298.6 µW, resulting in an energy efficiency of 94.74 fJ/conversion-step. The core circuit layout only occupies 0.017 mm2.

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