The RAW benchmark suite: computation structures for general purpose computing
暂无分享,去创建一个
Victor Lee | Rajeev Barua | Anant Agarwal | Jang Kim | Matthew I. Frank | Michael Bedford Taylor | Jonathan Babb | Elliot Waingold | Devabhaktuni Srikrishna
[1] Trevor Joseph Bauer. The design of an efficient hardware subroutine protocol for FPGAs , 1994 .
[2] Daniel P. Lopresti,et al. Building and using a highly parallel programmable logic array , 1991, Computer.
[3] Carl Ebeling,et al. Mapping applications to the RaPiD configurable architecture , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).
[4] P. Bertin,et al. PAM programming environments: practice and experience , 1994, Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines.
[5] Eduardo Juárez Martínez,et al. Architecture of a FPGA-based coprocessor: the PAR-1 , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.
[6] Richard J. Carter,et al. Teramac-configurable custom computing , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.
[7] Anant Agarwal,et al. Solving graph problems with dynamic computation structures , 1996, Other Conferences.
[8] Anant Agarwal,et al. Virtual wires: overcoming pin limitations in FPGA-based logic emulators , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.
[9] Donald E. Thomas,et al. The Verilog® Hardware Description Language , 1990 .
[10] Keigo Iizuka,et al. The Fast Fourier Transform (FFT) , 2019, Engineering Optics.
[11] Richard J. Carter,et al. Teramac configurable custom computer , 1995, Optics East.
[12] Eduardo Sanchez,et al. Spyder: a reconfigurable VLIW processor using FPGAs , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.
[13] Vivek Sarkar,et al. Baring it all to Software: The Raw Machine , 1997 .
[14] Dawson R. Engler,et al. VCODE: a retargetable, extensible, very fast dynamic code generation system , 1996, PLDI '96.
[15] Art Lew,et al. A FCCM for dataflow (spreadsheet) programs , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.
[16] Wayne Luk,et al. Hardware acceleration of divide-and-conquer paradigms: a case study , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.
[17] Peter M. Athanas,et al. Computing kernels implemented with a wormhole RTR CCM , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).
[18] Paul Chow,et al. RACER: a reconfigurable constraint-length 14 Viterbi decoder , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.
[19] W. Luk. A declarative approach to incremental custom computing , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.
[20] John Wawrzynek,et al. Garp: a MIPS processor with a reconfigurable coprocessor , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).
[21] Charles P. Pfleeger,et al. Security in computing , 1988 .