Fault detection in a testable PLA with low overhead for production testing

A testable structure is presented for programmable logic arrays (PLAs) which is amenable to production testing. A low overhead structure is proposed to keep the kill area at the lowest value. This is achieved by using a single additional input line to the original PLA. Fault detection is based on a specific set of conditions which must be satisfied in the characteristic matrix and structure of the minimized PLA. The characteristics of the vectors in the test set are discussed. A two-phase test is used to supplement the basic test vector if the specified constraint in the minimized PLA structure is not met. Hardware overhead is lower than any other method found in the technical literature.<<ETX>>

[1]  Chin-Long Wey,et al.  On the design of a redundant programmable logic array (RPLA) , 1987 .

[2]  Sudhakar M. Reddy,et al.  On the Design of Testable Domino PLAs , 1985, International Test Conference.

[3]  S. Gai,et al.  Fault detection in programmable logic arrays , 1986, Proceedings of the IEEE.

[4]  Kozo Kinoshita,et al.  A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead , 1985, ITC.

[5]  Kozo Kinoshita,et al.  A Design of Programmable Logic Arrays with Universal Tests , 1981, IEEE Transactions on Computers.

[6]  Edward J. McCluskey,et al.  Lower Overhead Design for Testability of Programmable Logic Arrays , 1986, IEEE Transactions on Computers.

[7]  J.-Y. Jou A testable PLA design with low overhead and ease of test generation , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

[8]  Sudhakar M. Reddy,et al.  A New Approach to the Design of Testable PLA's , 1987, IEEE Transactions on Computers.

[9]  Lynn Conway,et al.  Introduction to VLSI systems , 1978 .

[10]  Leon I. Maissel,et al.  An Introduction to Array Logic , 1975, IBM J. Res. Dev..

[11]  Robert K. Brayton,et al.  Logic Minimization Algorithms for VLSI Synthesis , 1984, The Kluwer International Series in Engineering and Computer Science.

[12]  Vinod K. Agarwal Multiple Fault Detection in Programmable Logic Arrays , 1980, IEEE Transactions on Computers.

[13]  Javad Khakbaz,et al.  A Testable PLA Design with Low Overhead and High Fault Coverage , 1984, IEEE Transactions on Computers.

[14]  Fabrizio Lombardi,et al.  Location and identification for single and multiple faults in testable redundant PLAs for yield enhancement , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.