Comparison of SRAM and FF PUF in 65nm Technology

Hardware security is an essential tool in the prevention of cloning, theft of service and tampering. This security is often based on cryptographic primitives, which use a key that is securely stored somewhere in the hardware. The strength of the security is therefore dependent upon the effort required from an attacker to compromise this key. Since the tools used to carry out attacks on hardware have increased significantly over the years, the protection provided by simply storing a key in memory has decreased to a minimum. In order to protect devices against attacks on their keys, Hardware Intrinsic Security (HIS) can be used. One of the best known types of HIS primitives are Physically Unclonable Functions (PUFs). PUFs are primitives that extract secrets from physical characteristics of integrated circuits (ICs) and can be used, amongst others, in secure key storage implementations. This paper describes the results of our study on two important types of intrinsic PUFs, based on SRAM and D flip-flops. Both memory types present a specific start-up pattern (when powered up), which can be used as a PUF. For secure practical applications, a PUF should possess enough reliability for a single device and enough randomness between different devices. In this paper, a general test framework is proposed for measuring this reliability and randomness of both PUF types. Based on this framework, tests have been performed on PUFs in 65nm ICs and results are presented and compared between PUF types. From these results it can be concluded that SRAMs are slightly outperforming D flip-flop memories when it comes to usage for PUF implementations.

[1]  R. Pappu,et al.  Physical One-Way Functions , 2002, Science.

[2]  Rafail Ostrovsky,et al.  Fuzzy Extractors: How to Generate Strong Keys from Biometrics and Other Noisy Data , 2004, SIAM J. Comput..

[3]  Frans M. J. Willems,et al.  The context-tree weighting method: basic properties , 1995, IEEE Trans. Inf. Theory.

[4]  Srinivas Devadas,et al.  Silicon physical random functions , 2002, CCS '02.

[5]  Ingrid Verbauwhede,et al.  Cryptographic Hardware and Embedded Systems - CHES 2007, 9th International Workshop, Vienna, Austria, September 10-13, 2007, Proceedings , 2007, CHES.

[6]  Helena Handschuh,et al.  Hardware intrinsic security from D flip-flops , 2010, STC '10.

[7]  David Naccache,et al.  Towards Hardware-Intrinsic Security - Foundations and Practice , 2010, Information Security and Cryptography.

[8]  Boris Skoric,et al.  Security with Noisy Data: Private Biometrics, Secure Key Storage and Anti-Counterfeiting , 2007 .

[9]  Elaine B. Barker,et al.  Recommendation for Random Number Generation Using Deterministic Random Bit Generators , 2007 .

[10]  Mario Konijnenburg,et al.  Evaluation of 90nm 6T-SRAM as Physical Unclonable Function for secure key generation in wireless sensor nodes , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[11]  John Kelsey,et al.  NIST Special Publication 800-90A: Recommendation for Random Number Generation Using Deterministic Random Bit Generators , 2011 .

[12]  Jorge Guajardo,et al.  FPGA Intrinsic PUFs and Their Use for IP Protection , 2007, CHES.

[13]  Ingrid Verbauwhede,et al.  Intrinsic PUFs from Flip-flops on Reconfigurable Devices , 2008 .

[14]  Elisabeth Oswald,et al.  Cryptographic Hardware and Embedded Systems - CHES 2008, 10th International Workshop, Washington, D.C., USA, August 10-13, 2008. Proceedings , 2008, CHES.

[15]  Ahmad-Reza Sadeghi,et al.  Efficient Helper Data Key Extractor on FPGAs , 2008, CHES.

[16]  Jorge Guajardo,et al.  Extended abstract: The butterfly PUF protecting IP on every FPGA , 2008, 2008 IEEE International Workshop on Hardware-Oriented Security and Trust.

[17]  Marten van Dijk,et al.  A technique to build a secret key in integrated circuits for identification and authentication applications , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).