Instruction based power consumption estimation methodology

The paper presents a new model of the dynamic power dissipated by a circuit described at gate or behavioural level. A procedure is presented for an accurate estimate of the power dissipated during the execution of each instruction by using gate level or behavioural level digital simulations. The information on power consumption stored in a look-up table can be used in a system level simulation. The methodology has been applied to the design of an I/sup 2/C bus driver.