A Formal Approach to Accountability in Heterogeneous Systems-on-Chip

Systems-on-chip (SoCs) are increasingly being composed of designs provided by different organizations. When such an SoC miscomputes or performs below expectation in-field, it is unclear which of the on-chip components caused the failure. The customer would like to use SoCs that provide the property of accountability, wherein the failure-causing component, and consequently its designing organization, can be unambiguously detected. Since it is a matter of trust, the various parties involved desire formal guarantees regarding any accountability solution. The solution must find the guilty component(s) in the event of a chip failure. Additionally, the solution must not falsely implicate any component that functioned correctly. This paper formally describes the property of accountability, a formal methodology of constructing an accountability solution, and a formal gametheory based methodology to reason about and prove the viability of a proposed solution. We explore the entire space of solutions, and characterize the attack surface and methods to provide accountability for each setting. We show non-intuitive results in this paper where seemingly simple solutions actually provide very powerful theoretical guarantees in terms of accountability.

[1]  Alptekin Küpçü,et al.  Incentivized Outsourced Computation Resistant to Malicious Contractors , 2017, IEEE Transactions on Dependable and Secure Computing.

[2]  Kees G. W. Goossens,et al.  Transaction-Based Communication-Centric Debug , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[3]  Lisa Spainhower,et al.  IBM S/390 Parallel Enterprise Server G5 fault tolerance: A historical perspective , 1999, IBM J. Res. Dev..

[4]  Jianying Zhou,et al.  An intensive survey of fair non-repudiation protocols , 2002, Comput. Commun..

[5]  Smruti R. Sarangi,et al.  A survey of checker architectures , 2013, CSUR.

[6]  Jeyavijayan Rajendran,et al.  Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security- Driven Task Scheduling , 2013, IEEE Transactions on Emerging Topics in Computing.

[7]  P. Mishra,et al.  Post-Silicon Validation and Debug , 2019 .

[8]  Wolfgang Rosenstiel,et al.  Measurement of IP qualification costs and benefits , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[9]  Todd M. Austin,et al.  DIVA: a reliable substrate for deep submicron microarchitecture design , 1999, MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture.

[10]  Ranjani Parthasarathi,et al.  A Survey on Post-Silicon Functional Validation for Multicore Architectures , 2017, ACM Comput. Surv..

[11]  Preeti Ranjan Panda,et al.  DHOOM: Reusing Design-for-Debug Hardware for Online Monitoring , 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

[12]  Smruti R. Sarangi,et al.  Managing Trace Summaries to Minimize Stalls During Postsilicon Validation , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Chase Qishi Wu,et al.  A Survey of Game Theory as Applied to Network Security , 2010, 2010 43rd Hawaii International Conference on System Sciences.

[14]  K. Xiao,et al.  Hardware Trojans , 2016, ACM Trans. Design Autom. Electr. Syst..

[15]  Smruti R. Sarangi,et al.  SecX: A Framework for Collecting Runtime Statistics for SoCs with Multiple Accelerators , 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

[16]  Swarup Bhunia,et al.  Exploiting design-for-debug for flexible SoC security architecture , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[17]  G. Edward Suh,et al.  Physical Unclonable Functions for Device Authentication and Secret Key Generation , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[18]  Jeyavijayan Rajendran,et al.  High-level synthesis for security and trust , 2013, 2013 IEEE 19th International On-Line Testing Symposium (IOLTS).

[19]  Jonathan Graf.  Trust games: How game theory can guide the development of hardware Trojan detection methods , 2016, 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[20]  Sally Adee,et al.  The Hunt For The Kill Switch , 2008, IEEE Spectrum.

[21]  Smruti R. Sarangi,et al.  Providing Accountability in Heterogeneous Systems-on-Chip , 2018, ACM Trans. Embed. Comput. Syst..

[22]  Neal Stollon.  On-Chip Instrumentation: Design and Debug for Systems on Chip , 2010 .

[23]  Miron Abramovici,et al.  Integrated circuit security: new threats and solutions , 2009, CSIIRW '09.

[24]  Ankur Srivastava,et al.  Introducing TFUE: The trusted foundry and untrusted employee model in IC supply chain security , 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

[25]  Lawrence T. Pileggi,et al.  Building trusted ICs using split fabrication , 2014, 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

[26]  Katerina J. Argyraki,et al.  Loss and Delay Accountability for the Internet , 2007, 2007 IEEE International Conference on Network Protocols.

[27]  Andrey Bogdanov,et al.  PRESENT: An Ultra-Lightweight Block Cipher , 2007, CHES.

[28]  Mark Mohammad Tehranipoor,et al.  Case study: Detecting hardware Trojans in third-party digital IP cores , 2011, 2011 IEEE International Symposium on Hardware-Oriented Security and Trust.

[29]  Samir Chouali,et al.  SysML Blocks Adaptation , 2015, ICFEM.

[30]  Bart Vermeulen.  Functional Debug Techniques for Embedded Systems , 2008, IEEE Design & Test of Computers.

[31]  Daniel D. Gajski,et al.  Embedded tutorial: essential issues for IP reuse , 2000, ASP-DAC '00.

[32]  John Villasenor,et al.  Chop shop electronics , 2013, IEEE Spectrum.

[33]  Mark Mohammad Tehranipoor,et al.  Comparative Analysis of Hardware Obfuscation for IP Protection , 2017, ACM Great Lakes Symposium on VLSI.

[34]  Li-wei Wang,et al.  Automated IP quality qualification for efficient system-on-chip design , 2012, 2012 13th International Conference on Electronic Packaging Technology & High Density Packaging.