Sampling holding circuit applied to high-speed high-precision circuit

The invention discloses a sampling holding circuit applied to a high-speed high-precision circuit. The sampling holding circuit comprises a full-differential type operational amplifier, two sampling capacitors Cs, two sampling switches S1 and five selective switches and a low-pass filter circuit formed by a resistor R1 and a capacitor C1. The full-differential type operational amplifier is a gain enhancement folding cascade full-differential type operational amplifier, a sampling switch S1 is a grid voltage bootstrap switch, connected structures of the positive end and the negative end of the full-differential type operational amplifier are completely same, and a signal input end passes through the low-pass filter circuit to be connected with a lower pole plate of the sampling capacitors Cs through the sampling switches S1. A selective switch S3 is connected with the lower pole plate of the sampling capacitors Cs and the output end of the full-differential type operational amplifier. An upper pole plate of the sampling capacitors Cs is connected with the input end of the full-differential type operational amplifier, a selective switch S4 is connected with upper pole plates of the two sampling capacitors Cs, and a selective switch S2 is connected with the input end and the output end of the full-differential type operational amplifier. The sampling holding circuit can achieve sampling holding of the input signals in the high-speed high-precision circuit.