Comparative $\eta$– $\rho$– $\sigma$ Pareto Optimization of Si and SiC Multilevel Dual-Active-Bridge Topologies With Wide Input Voltage Range

This work presents a comprehensive cost-aware comparison of isolated bidirectional Si and SiC dual-active-bridge (DAB) concepts for a 5-kW 100–700-V input voltage range dc microgrid application. A conventional three-level DAB (3LDAB) is compared to an advanced five-level DAB (5LDAB) topology, where the latter enables reduced rms currents within the given voltage range. Both concepts employ a loss-optimized modulation scheme enabling zero-voltage switching. A multiobjective optimization routine is proposed to systematically assess the concepts with respect to the efficiency, power density, and the costs. A novel waveform model and advanced component models are considered, which are verified using a hardware prototype. The calculated Pareto fronts show that SiC MOSFETs enable significantly higher efficiencies and power densities than Si IGBTs, while similar costs can be achieved. The performance comparison between the SiC MOSFET-based 3LDAB and 5LDAB reveals a fundamental superiority of the 3LDAB, which is mainly due to the higher chip area utilization and the lower component count of this concept. Finally, the calculations and the hardware prototype prove that despite the galvanic isolation and wide voltage range, efficiencies above 98 % in a wide operating range are possible, which was previously not seen in the literature.