Digital techniques for improved /spl Delta//spl Sigma/ data conversion

Two digital techniques are described in this tutorial, both aimed at improving the accuracy of delta-sigma data converters. The first one corrects adaptively for mismatch errors in a MASH ADC, while the other acquires and then corrects for the nonlinearity of the internal multibit DAC used in the ADC.

[1]  Gabor C. Temes,et al.  Adaptive selfcalibrating delta-sigma modulators , 1992 .

[2]  Gabor C. Temes,et al.  On-line adaptive digital correction of dual-quantisation delta-sigma modulators , 1992 .

[3]  Ángel Benito Rodríguez Vázquez,et al.  A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology , 1999 .

[4]  G.C. Temes,et al.  Adaptive compensation of analog circuit imperfections for cascaded /spl Sigma//spl Delta/ modulators , 1996, Conference Record of The Thirtieth Asilomar Conference on Signals, Systems and Computers.

[5]  Gabor C. Temes,et al.  Improved Adaptive Digital Compensation for Cascaded Delta-Sigma ADCs , 2000 .

[6]  Un-Ku Moon,et al.  Adaptive digital correction of analog errors in MASH ADCs. II. Correction using test-signal injection , 2000 .

[7]  Gabor C. Temes,et al.  A high-resolution multibit Sigma Delta ADC with digital correction and relaxed amplifier requirements , 1993 .

[8]  T. C. Leslie,et al.  An improved sigma-delta modulator architecture , 1990, IEEE International Symposium on Circuits and Systems.

[9]  Jesper Steensgaard-Madsen,et al.  High-Performance Data Converters , 1999 .

[10]  Gabor C. Temes,et al.  Improved SignaltoNoise Ratio Using TriLevel DeltaSigma Modulation , 1992 .

[11]  Xieting Ling,et al.  Sigma-delta ADC with reduced sample rate multibit quantizer , 1999 .

[12]  W. Sansen,et al.  A 3.3 V 15-bit delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL-applications , 1999, Proceedings of the 24th European Solid-State Circuits Conference.

[13]  Sanjit K. Mitra,et al.  Block implementation of adaptive digital filters , 1981 .

[14]  G. Temes Delta-sigma data converters , 1994 .

[15]  R. Schreier,et al.  Delta-sigma data converters : theory, design, and simulation , 1997 .

[16]  Stephen H. Lewis,et al.  A 10-b 20-Msample/s analog-to-digital converter , 1992 .

[17]  Gert Cauwenberghs,et al.  Adaptive digital correction of analog errors in MASH ADCs. I. Off-line and blind on-line calibration , 2000 .

[18]  B. A. Minch,et al.  IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing , 1998 .

[19]  G. Temes,et al.  Wideband low-distortion delta-sigma ADC topology , 2001 .

[20]  Gabor C. Temes,et al.  Adaptive compensation of analog circuit imperfections for cascaded delta-sigma ADCs , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[21]  Todd L. Brooks,et al.  A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR , 1997 .

[22]  Gert Cauwenberghs,et al.  Adaptive calibration of multiple quantization oversampled A/D converters , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[23]  Belén Pérez-Verdú,et al.  A 13-bit, 2.2-MS/s, 55-mW multibit cascade /spl Sigma//spl Delta/ modulator in CMOS 0.7-/spl mu/m single-poly technology , 1999 .

[24]  Michel Steyaert,et al.  Optimal parameters for /spl Delta//spl Sigma/ modulator topologies , 1998 .

[25]  Tao Sun Compensation techniques for cascaded delta-sigma A/D converters and high-performance switched-capacitor circuits , 1998 .