of a Fast Intra Prediction Algorithm for H.264/ A VC Encoding

Intra-frame coding is one of the most important technologies in H.264/A ve, which made significant contributions to the enhancement of coding efficiency of H.264/A ve at the cost of computation complexity. To address this problem, in this paper we present an efficient VLSI implementation of a computation efficient intra prediction algorithm for H.264/AVe encoding. Unlike most of existing fast intra-mode selection techniques, in the proposed method the directional differences are computed using a few selected original pixels to obtain the candidate modes with the minimal direction cost. The proposed method is hardware-friendl y and provides more processing parallelism for H.264 intra-frame encoding with less overhead and less power consumption, which is expected to be utilized as a favourable accelerator hardware module in a real-time HDTV (1920xl080p) H.264 encoder. intra prediction method with the corresponding VLSI implementation in this paper. Unlike most of existing fast intra-mode selection techniques, in the proposed method the directional differences are computed using a few selected original pixels to obtain the candidate mode with the minimal directional cost, which makes it more suitable to be implemented in hardware. When compared with the reference software JMlO.2, on average the proposed method can achieve +O.OI5db improvement with 1.6% of bit rate increase. The final implemented design can achieve HDTV size intra video encoding, running at 140MHz, and achieving a speedup of 4X when compared with previous works. The rest of this paper is organized as follows. The proposed computation efficient intra prediction algorithm is introduced in Section II with the simulation results. Section III shows the corresponding VLSI implementation of the proposed method, and fmally our work is concluded in Section IV.