Design of improved‐reliability nanocircuits with mixed NBTI‐ and HCI‐aware gate‐sizing formulation

Non-memberNegative bias temperature instability (NBTI) and hot carrier injection (HCI) are two important processes of reliability concernin nano-scale integrated circuits. A circuit-level design technique to combat NBTI degradation is gate oversizing. This paperpresents a new technique based on PMOS and NMOS resistance variation for the NBTI- and HCI-aware gate-sizing problem forthe first time. In this technique, the area of the circuit is minimized with constraints on degraded delay due to NBTI and HCI andthe transitor size. Expreimental results for several gates and ISCAS’85 benchmark circuits show that this technique imposes anarea overhead of less than 1% with respect to baseline design in most cases. © 2013 Institute of Electrical Engineers of Japan.Published by John Wiley & Sons, Inc.

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