Automated area and coverage optimization of minimal latency checkers

With the scaling of silicon technology beyond the sub-micron domain, the probability of the system being exposed to different sources of faults increases. Manifestation of new defects during system's run-time, necessitates the need for a mechanism providing cost-effective online fault detection which performs concurrently with the circuit's normal operation and has low area overhead and high fault coverage. Especially crucial is the fault detection latency, as the system's ability to isolate faults and recover from them is highly dependent on the detection time. This paper proposes two heuristics (branch-and-bound and greedy) for minimization of concurrent online checkers. Both algorithms use the concept of dominant checkers, proposed in this work. The method allows generating minimal area checkers satisfying a target fault coverage with the shortest possible fault detection latency. Experimental results demonstrate the area efficiency of the approach compared to other methods.