An Introduction to Multi-Core System on Chip - Trends and Challenges
暂无分享,去创建一个
Fabien Clermidy | Pascal Benoit | Lionel Torres | Michel Robert | Diego Puschini | Gilles Sassatelli
[1] Markus Rupp,et al. Task Scheduling for Power Optimisation of Multi Frequency Synchronous Data Flow Graphs , 2005, 2005 18th Symposium on Integrated Circuits and Systems Design.
[2] Santanu Dutta,et al. Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems , 2001, IEEE Des. Test Comput..
[3] Ira Krepchin,et al. Texas Instruments Inc. , 1963, Nature.
[4] Davide Rossi,et al. A heterogeneous digital signal processor implementation for dynamically reconfigurable computing , 2009, 2009 IEEE Custom Integrated Circuits Conference.
[5] Bryan D. Ackland,et al. A single-chip 1.6 billion 16-b MAC/s multiprocessor DSP , 1999 .
[6] Tobias Bjerregaard,et al. A survey of research and practices of Network-on-chip , 2006, CSUR.
[7] Stephen P. Boyd,et al. Temperature-aware processor frequency assignment for MPSoCs using convex optimization , 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).
[8] Yusuf Leblebici,et al. Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation , 2006, 2006 IFIP International Conference on Very Large Scale Integration.
[9] Tajana Rosing,et al. Temperature aware task scheduling in MPSoCs , 2007 .
[10] Yusuf Leblebici,et al. On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation , 2006 .
[11] Ahmed Amine Jerraya,et al. Multiprocessor System-on-Chip (MPSoC) Technology , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[12] Chantal Ykman-Couvreur,et al. Pareto-Based Application Specification for MP-SoC Customized Run-Time Management , 2006, 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation.
[13] Fabien Clermidy,et al. An asynchronous NOC architecture providing low latency service and its multi-level design framework , 2005, 11th IEEE International Symposium on Asynchronous Circuits and Systems.
[14] H. Corporaal,et al. Design-Time Application Exploration for MP-SoC Customized Run-Time Management , 2005, 2005 International Symposium on System-on-Chip.
[15] Wayne H. Wolf,et al. Multiprocessor Systems-on-Chips , 2004, ISVLSI.
[16] Matheus T. Moreira,et al. Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques , 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.
[17] Narayanan Vijaykrishnan,et al. Hotspot prevention through runtime reconfiguration in network-on-chip , 2005, Design, Automation and Test in Europe.
[18] William J. Dally,et al. Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.
[19] Fabien Clermidy,et al. Adaptive energy-aware latency-constrained DVFS policy for MPSoC , 2009, 2009 IEEE International SOC Conference (SOCC).
[20] D. Marculescu,et al. Speed and voltage selection for GALS systems based on voltage/frequency islands , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..
[21] Hannu Tenhunen,et al. Guest Editors' Introduction: Multiprocessor Systems-on-Chips , 2005, Computer.
[22] Luca Benini,et al. Networks on Chips : A New SoC Paradigm , 2022 .
[23] Michael J. Flynn,et al. Some Computer Organizations and Their Effectiveness , 1972, IEEE Transactions on Computers.
[24] Paul Feautrier,et al. Methods for power optimization in SOC-based data flow systems , 2009, TODE.
[25] H. Corporaal,et al. Fast Multi-Dimension Multi-Choice Knapsack Heuristic for MP-SoC Run-Time Management , 2006, 2006 International Symposium on System-on-Chip.
[26] Fernando Gehm Moraes,et al. Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs , 2007, 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07).
[27] Radu Marculescu,et al. Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[28] Alain Greiner,et al. A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.
[29] Fabien Clermidy,et al. Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC , 2008 .
[30] Edward A. Lee,et al. Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing , 1989, IEEE Transactions on Computers.
[31] Tajana Simunic,et al. Temperature-aware MPSoC scheduling for reducing hot spots and gradients , 2008, 2008 Asia and South Pacific Design Automation Conference.
[32] Fabien Clermidy,et al. A Game-Theoretic Approach for Run-Time Distributed Optimization on MP-SoC , 2008, Int. J. Reconfigurable Comput..
[33] G.E. Moore,et al. Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.
[34] Yusuf Leblebici,et al. Analysis and Optimization of MPSoC Reliability , 2006, J. Low Power Electron..
[35] Fabien Clermidy,et al. Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game Theory , 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.
[36] L. Benini,et al. Xpipes: a network-on-chip architecture for gigascale systems-on-chip , 2004, IEEE Circuits and Systems Magazine.
[37] Partha Pratim Pande,et al. Performance evaluation and design trade-offs for network-on-chip interconnect architectures , 2005, IEEE Transactions on Computers.
[38] Mohamed Abid,et al. System Level Design Space Exploration for Multiprocessor System on Chip , 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.
[39] Wayne H. Wolf. The future of multiprocessor systems-on-chips , 2004, Proceedings. 41st Design Automation Conference, 2004..
[40] Luca Benini,et al. Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization , 2008, 2008 Design, Automation and Test in Europe.
[41] Herman H. Goldstine,et al. Preliminary discussion of the logical design of an electronic computing instrument (1946) , 1989 .