论文信息 - Modeling and evaluation for electrical characteristics of through-strata-vias (TSVS) in three-dimensional integration

Modeling and evaluation for electrical characteristics of through-strata-vias (TSVS) in three-dimensional integration

This paper discusses through-strata-vias (TSVs) technology and presents modeling results of their electrical performance using Agilent's ADS and Momentum simulator. Since TSV is an essential component in three-dimensional (3D) integration/packaging, it is important to explore and investigate its electrical characteristics. A simple face-to-back TSV is studied in frequency domain and time domain. The impact of physical configurations and materials on TSV electrical characteristics is evaluated. An equivalent circuit model is proposed, and the values of passive elements (resistance, inductance and capacitance) within the model are extracted from full-wave scattering parameters.

[1] Jian-Qiang Lu,et al. 3-D Hyperintegration and Packaging Technologies for Micro-Nano Systems , 2009, Proceedings of the IEEE.

[2] Herbert Reichl,et al. Thermo-Mechanical Reliability of 3D-integrated Microstructures in Stacked Silicon , 2006 .

[3] V. Lee,et al. Development of 3D silicon module with TSV for system in packaging , 2008, 2008 58th Electronic Components and Technology Conference.

[4] Robert S. Patti. Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs In 3D integrated circuits, analog, digital, flash and DRAM wafers are processed separately, then brought together in an integrated vertical stack. , 2006 .

[5] Phillp Garrou. 3-D ICs Enter Commercialization , 2008 .

[6] P. Andry,et al. CMOS-Compatible Through Silicon Vias for 3D Process Integration , 2006 .

[7] L. Leung,et al. Microwave characterization and modeling of high aspect ratio through-wafer interconnect vias in silicon substrates , 2005, IEEE Transactions on Microwave Theory and Techniques.

[8] Eby G. Friedman,et al. Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits , 2009, Proceedings of the IEEE.

[9] Muhannad S. Bakir,et al. Integrated Interconnect Technologies for 3D Nanoelectronic Systems , 2008 .

[10] Robert S. Patti,et al. Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs , 2006, Proceedings of the IEEE.