A novel approach for high-frequency pipelined A/D conversion

Flash and parallel approaches are compared with the pipeline solution, and the advantages of the latter technique are evaluated. A pipeline design is examined extensively, and circuit improvements suitable for increasing conversion speed are described. The proposed scheme includes a self-calibration to compensate conversion errors, in particular the error resulting from the use of very fast op-amps with low DC gain. A novel approach for speeding up the pipeline converter, referred to as digital assisted slewing is proposed.<<ETX>>

[1]  Anil K. Jain,et al.  Image data compression: A review , 1981, Proceedings of the IEEE.

[2]  Gabor C. Temes.  High-accuracy pipeline A/D convertor configuration , 1985 .

[3]  D.A. Hodges,et al.  A self-calibrating 15 bit CMOS A/D converter , 1984, IEEE Journal of Solid-State Circuits.

[4]  W. Black,et al.  Time interleaved converter arrays , 1980, 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[5]  W. Black,et al.  An algorithmic analog-to-digital converter , 1977, 1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[6]  A. Dingwall,et al.  An 8-MHz CMOS subranging 8-bit A/D converter , 1985, IEEE Journal of Solid-State Circuits.