Analysis of Modified Feed-Through Logic with Improved Power Delay Product

A modified approach for Feed-Through logic (FTL) is developed in this paper to provide improved power delay product (PDP). FTL is examined against proposed approach, by analysis through computer simulation. It is shown that the modified FTL has low power consumption and high speed over existing FTL. Based on the performance the given approach is found very efficient for high speed arithmetic or pipelining circuit. Furthermore, the sensitivity of both the approaches is investigated against power supply and capacitive load. Investigation suggests that the given approach has improved delay product over FTL.

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