2-D analysis of the negative resistance region of vertical power MOS-transistors

Vertical Power SIPMOS MOS transistors are realized as multitransistors with parallel source and gate structures using N-epi and heavily doped substrate as common drain. The terminal characteristic of these devices typically show a negative resistance region which is increasingly pronounced in case of higher gate voltages. In order to optimize layout and design of such structures 2-D simulations as well as measurements have been carried out. The relevant mechanism causing the negative resistance region has been identified and measurements as well as a model facilitating design is presented. Consequences are discussed including breakdown and temperature effects.