Kernel Extraction for Watermarking Combinational Logic Networks

Timing slacks of a synthesized design can be used to identify some local networks for embedding watermark information to achieve the goal of IP protection. The identification of suitable local networks plays a key role to ensure that the watermarked design can still meet the constraints from the original synthesized result. We propose a method to select the kernels according to the anticipatory global effect caused by their remapping. The design is updated progressively by retaining or remapping the newly found kernel according to the stego-signature bit to be embedded before seeking for the next kernel. We have tested this method on a set of MCNC combinational benchmarks. Experimental results show that for as long as the original design size is not too small, our method can extract enough kernels for watermark insertion with trivial overhead and guaranteed timing convergence

[1]  Edoardo Charbon Hierarchical watermarking in IC design , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[2]  Miodrag Potkonjak,et al.  Local watermarks: methodology and application to behavioral synthesis , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Chip-Hong Chang,et al.  Fuzzy-ART based adaptive digital watermarking scheme , 2005, IEEE Transactions on Circuits and Systems for Video Technology.

[4]  Miodrag Potkonjak,et al.  Techniques for intellectual property protection of DSP designs , 1998, Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '98 (Cat. No.98CH36181).

[5]  Jason Cong,et al.  Intellectual property protection by watermarking combinational logic synthesis solutions , 1998, ICCAD '98.

[6]  Miodrag Potkonjak,et al.  Constraint-based watermarking techniques for design IP protection , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Chip-Hong Chang,et al.  Stego-signature at logic synthesis level for digital design IP protection , 2006, 2006 IEEE International Symposium on Circuits and Systems.