Analog/RF IP Protection: Attack Models, Defense Techniques, and Challenges

The globalized and distributed semiconductor supply chain exposes the integrated circuits to security threats. These threats can target the circuit functionality, the secret data processed by the circuit, or the design’s intellectual property (IP). Multiple commercial devices include dedicated hardware root-of-trust for performing security tasks. These approaches protect digital circuits but ignore the vulnerabilities of analog circuits. Recently, researchers have proposed techniques to protect the IP of analog circuits. This brief systematizes the knowledge of analog IP protection. It gives an overview of the reported threat models, defense techniques, and attacks targeting analog/RF circuits.

[1]  Ramesh Karri,et al.  A Primer on Hardware Security: Models, Methods, and Metrics , 2014, Proceedings of the IEEE.

[2]  Omar Alrawi,et al.  SoK: Security Evaluation of Home-Based IoT Deployments , 2019, 2019 IEEE Symposium on Security and Privacy (SP).

[3]  Jeyavijayan Rajendran,et al.  Provably-Secure Logic Locking: From Theory To Practice , 2017, CCS.

[4]  Ioannis Savidis,et al.  Transistor Sizing for Parameter Obfuscation of Analog Circuits Using Satisfiability Modulo Theory , 2018, 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

[5]  Ankur Srivastava,et al.  Mitigating SAT Attack on Logic Locking , 2016, CHES.

[6]  Franziska Hoffmann,et al.  Design Of Analog Cmos Integrated Circuits , 2016 .

[7]  Jeyavijayan Rajendran,et al.  Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction , 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[8]  Ioannis Savidis,et al.  Securing Analog Mixed-Signal Integrated Circuits Through Shared Dependencies , 2019, ACM Great Lakes Symposium on VLSI.

[9]  Yiorgos Makris,et al.  Trusted and Secure Design of Analog/RF ICs: Recent Developments , 2019, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS).

[10]  Hassan Aboushady,et al.  Analog and Mixed-Signal IC Security via Sizing Camouflaging , 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Congyin Shi,et al.  A Built-In Self-Test and In Situ Analog Circuit Optimization Platform , 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Abdullah Ash-Saki,et al.  How Multi-Threshold Designs Can Protect Analog IPs , 2018, 2018 IEEE 36th International Conference on Computer Design (ICCD).

[13]  Ozgur Sinanoglu,et al.  Mixed-Signal Hardware Security Using MixLock: Demonstration in an Audio Application , 2019, 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

[14]  Domenic Forte,et al.  Novel Bypass Attack and BDD-based Tradeoff Analysis Against All Known Logic Locking Attacks , 2017, CHES.

[15]  LiMeng,et al.  IP Protection and Supply Chain Security through Logic Obfuscation , 2019 .

[16]  Dick James,et al.  The state-of-the-art in semiconductor reverse engineering , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[17]  Yiorgos Makris,et al.  Security and trust in the analog/mixed-signal/RF domain: A survey and a perspective , 2017, 2017 22nd IEEE European Test Symposium (ETS).

[18]  Randall L. Geiger,et al.  Hardware Trojans embedded in the dynamic operation of analog and mixed-signal circuits , 2015, 2015 National Aerospace and Electronics Conference (NAECON).

[19]  Jeyavijayan Rajendran,et al.  Security analysis of integrated circuit camouflaging , 2013, CCS.

[20]  Yiorgos Makris,et al.  Analog Performance Locking through Neural Network-Based Biasing , 2019, 2019 IEEE 37th VLSI Test Symposium (VTS).

[21]  Miodrag Potkonjak,et al.  Watermarking techniques for intellectual property protection , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[22]  Chih-Sheng Chang,et al.  Advanced CMOS technology portfolio for RF IC applications , 2005, IEEE Transactions on Electron Devices.

[23]  Mark Mohammad Tehranipoor,et al.  Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain , 2014, Proceedings of the IEEE.

[24]  Farinaz Koushanfar,et al.  Active Hardware Metering for Intellectual Property Protection and Security , 2007, USENIX Security Symposium.

[25]  Congyin Shi,et al.  Built-In Self Optimization for Variation Resilience of Analog Filters , 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

[26]  Ioannis Savidis,et al.  Mesh Based Obfuscation of Analog Circuit Properties , 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

[27]  Rob A. Rutenbar,et al.  Design Automation for Analog: The Next Generation of Tool Challenges , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[28]  Ozgur Sinanoglu,et al.  MixLock: Securing Mixed-Signal Circuits via Logic Locking , 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[29]  G. Edward Suh,et al.  Physical Unclonable Functions for Device Authentication and Secret Key Generation , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[30]  Yiorgos Makris,et al.  Range-Controlled Floating-Gate Transistors: A Unified Solution for Unlocking and Calibrating Analog ICs , 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[31]  Jeyavijayan Rajendran,et al.  Breaking Analog Locking Techniques , 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[32]  Congyin Shi,et al.  Thwarting analog IC piracy via combinational locking , 2017, 2017 IEEE International Test Conference (ITC).

[33]  Michael S. Hsiao,et al.  Hardware Trojan Attacks: Threat Analysis and Countermeasures , 2014, Proceedings of the IEEE.

[34]  Massimo Alioto,et al.  Trends in Hardware Security: From basics to ASICs , 2019, IEEE Solid-State Circuits Magazine.

[35]  Sayak Ray,et al.  Evaluating the security of logic encryption algorithms , 2015, 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[36]  Jeyavijayan Rajendran,et al.  Security analysis of logic obfuscation , 2012, DAC Design Automation Conference 2012.

[37]  A. Sanabria-Borbón,et al.  Schmitt Trigger-Based Key Provisioning for Locking Analog/RF Integrated Circuits , 2020, 2020 IEEE International Test Conference (ITC).

[38]  Jarrod A. Roy,et al.  Ending Piracy of Integrated Circuits , 2010, Computer.

[39]  Wenyuan Xu,et al.  DolphinAttack: Inaudible Voice Commands , 2017, CCS.

[40]  Randall L. Geiger,et al.  Hardware trojan state detection for analog circuits and systems , 2014, NAECON 2014 - IEEE National Aerospace and Electronics Conference.

[41]  Domenic Forte,et al.  Attack of the Genes: Finding Keys and Parameters of Locked Analog ICs Using Genetic Algorithm , 2020, 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[42]  Jeyavijayan Rajendran,et al.  Towards Secure Analog Designs: A Secure Sense Amplifier Using Memristors , 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

[43]  Farinaz Koushanfar,et al.  A Survey of Hardware Trojan Taxonomy and Detection , 2010, IEEE Design & Test of Computers.

[44]  Srinivas Devadas,et al.  Physical Unclonable Functions and Applications: A Tutorial , 2014, Proceedings of the IEEE.

[45]  Ioannis Savidis,et al.  Parameter biasing obfuscation for analog IP protection , 2017, 2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).