Noise-Coupled Image Rejection Architecture of Complex Bandpass ΔΣAD Modulator

This paper proposes a new realization technique of image rejection function by noise-coupling architecture, which is used for a complex bandpass ΔΣAD modulator. The complex bandpass ΔΣAD modulator processes just input I and Q signals, not image signals, and the AD conversion can be realized with low power dissipation. It realizes an asymmetric noise-shaped spectra, which is desirable for such low-IF receiver applications. However, the performance of the complex bandpass ΔΣAD modulator suffers from the mismatch between internal analog I and Q paths. I/Q path mismatch causes an image signal, and the quantization noise of the mirror image band aliases into the desired signal band, which degrades the SQNDR (Signal to Quantization Noise and Distortion Ratio) of the modulator. In our proposed modulator architecture, an extra notch for image rejection is realized by noise-coupled topology. We just add some passive capacitors and switches to the modulator; the additional integrator circuit composed of an operational amplifier in the conventional image rejection realization is not necessary. Therefore, the performance of the complex modulator can be effectively raised without additional power dissipation. We have performed simulation with MATLAB to confirm the validity of the proposed architecture. The simulation results show that the proposed architecture can achieve the realization of image-rejection effectively, and improve the SQNDR of the complex bandpass ΔΣAD modulator.

[1]  A Noise-Shaping Algorithm of Multi-bit DAC Nonliearities in Complex Bandpass ∆ΣAD Modulators , 2003 .

[2]  K. Martin,et al.  Complex signal processing is not-complex , 2003, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..

[3]  Haruo Kobayashi,et al.  Complex bandpass ΔΣAD modulator with noise-coupled image rejection , 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.

[4]  A. Sedra,et al.  Quadrature bandpass /spl Delta//spl Sigma/ modulation for digital radio , 1997 .

[5]  S. Jantzi,et al.  A quadrature bandpass /spl Sigma//spl Delta/ modulator for digital radio , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[6]  Gabor C. Temes,et al.  Understanding Delta-Sigma Data Converters , 2004 .

[7]  K. Mashiko,et al.  Complex Bandpass ∆ΣAD Modulator Architecture Without I, Q-Path Crossing Layout , 2005 .

[8]  A. Sedra,et al.  The effects of mismatch in complex bandpass /spl Delta//spl Sigma/ modulators , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[9]  Gabor C. Temes,et al.  A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, ${-}$ 98 dB THD, and 79 dB SNDR , 2008, IEEE Journal of Solid-State Circuits.

[10]  Michiel Steyaert,et al.  Low-IF topologies for high-performance analog front ends of fully integrated receivers , 1998 .

[11]  R. Schreier,et al.  Mismatch shaping for a current-mode multibit delta-sigma DAC , 1999, IEEE J. Solid State Circuits.