Towards automatic partial reconfiguration in FPGAs
暂无分享,去创建一个
[1] Tobias Becker,et al. Modular partial reconfigurable in Virtex FPGAs , 2005, International Conference on Field Programmable Logic and Applications, 2005..
[2] P. Chow,et al. The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout , 1999, IEEE Trans. Very Large Scale Integr. Syst..
[3] David Dye. Partial Reconfiguration of Xilinx FPGAs Using ISE Design Suite , 2010 .
[4] Yao-Wen Chang,et al. Modern floorplanning based on B/sup */-tree and fast simulated annealing , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[5] Nan Liu,et al. Resource-Aware Multi-Layer Floorplanning for Partially Reconfigurable FPGAs , 2013, IEICE transactions on electronics.
[6] Kenneth B. Kent,et al. The VTR project: architecture and CAD for FPGAs from verilog to routing , 2012, FPGA '12.
[7] Wei Zhang,et al. BMP: a fast B*-tree based modular placer for FPGAs (abstract only) , 2014, FPGA.
[8] Susmita Sur-Kolay,et al. Floorplanning for Partially Reconfigurable FPGAs , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[9] Yao-Wen Chang,et al. Modern floorplanning based on fast simulated annealing , 2005, ISPD '05.