Scaling constraints imposed by self-heating in submicron SOI MOSFET's

The presence of a buried oxide layer in silicon causes enhanced self-heating in Silicon-On-Insulator (SOI) n-channel MOSFETs. The self-heating becomes more pronounced as device dimensions are reduced into the submicron regime because of increased electric field density and reduced silicon volume available for heat removal. Two-dimensional numerical simulations are used to show that self-heating manifests itself in the form of degraded drive current due to mobility reduction and premature breakdown. The heat flow equation was consistently solved with the classical semiconductor equations to study the effect of power dissipation on carrier transport. The simulated temperature increases in the channel region are shown to be in close agreement with recently measured data. Numerical simulation results also demonstrated accelerated turn-on of the parasitic bipolar transistor due to self-heating. Simulation results were used to identify scaling constraints caused by the parasitic bipolar transistor turn-on effect in SOI CMOS ULSI. For a quarter-micron n-channel SOI MOSFET, results suggest a maximum power supply of 1.8 V. In the deep submicron regime, SOI devices exhibited a negative differential resistance due to increased self-heating with drain bias voltage. Detailed comparison with bulk devices suggested significant reduction in the drain-source avalanche breakdown voltage due to increased carrier injection at the source-body junction. >

[1]  Y. Apanovich,et al.  Non-isothermal analysis of breakdown in SOI transistors , 1993 .

[2]  C. Hu,et al.  Room temperature observation of velocity overshoot in silicon inversion layers , 1993, Proceedings of 1993 IEEE International SOI Conference.

[3]  J. Fossum,et al.  Subthreshold MOSFET conduction model and optimal scaling for deep-submicron fully depleted SOI CMOS , 1993, Proceedings of 1993 IEEE International SOI Conference.

[4]  Jerry G. Fossum,et al.  Non-local modeling of impact ionization for optimal device/circuit design in fully depleted SOI CMOS technology , 1993, Proceedings of 1993 IEEE International SOI Conference.

[5]  Jerry G. Fossum,et al.  Analysis and control of floating-body bipolar effects in fully depleted submicrometer SOI MOSFET's , 1991 .

[6]  J. Colinge.  Silicon-on-Insulator Technology: Materials to VLSI , 1991 .

[7]  Gerhard K. M. Wachutka,et al.  Rigorous thermodynamic treatment of heat generation and conduction in semiconductor device modeling , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  E. Cortesi,et al.  Characterization of low energy SIMOX (LES) structures , 1990, 1990 IEEE SOS/SOI Technology Conference. Proceedings.

[9]  Steve Hall,et al.  Physical origin of negative differential resistance in SOI transistors , 1989 .

[10]  K. K. Young.  Analysis of conduction in fully depleted SOI MOSFETs , 1989 .

[11]  K. K. Young.  Short-channel effect in fully depleted SOI MOSFETs , 1989 .

[12]  N. Goldsman,et al.  Efficient and accurate use of the energy transport method in device simulation , 1988 .

[13]  Masaaki Tomizawa,et al.  Nonstationary carrier dynamics in quarter-micron Si MOSFETs , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  J. Colinge.  Reduction of kink effect in thin-film SOI MOSFETs , 1988, IEEE Electron Device Letters.

[15]  J. Colinge.  Subthreshold slope of thin-film SOI MOSFET's , 1986, IEEE Electron Device Letters.

[16]  D.K. Sharma,et al.  Modeling thermal effects on MOS I-V characteristics , 1983, IEEE Electron Device Letters.

[17]  J. Hauser,et al.  Electron and hole mobilities in silicon as a function of concentration and temperature , 1982, IEEE Transactions on Electron Devices.

[18]  Dinesh K. Sharma,et al.  Negative dynamic resistance in MOS devices , 1978 .

[19]  Kenneth E. Goodson,et al.  Measurement and modeling of self-heating in SOI nMOSFET's , 1994 .

[20]  J. Colinge.  Silicon-on-Insulator Technology , 1991 .

[21]  S. Selberherr.  Analysis and simulation of semiconductor devices , 1984 .

[22]  P. Mars,et al.  Temperature dependence of avalanche breakdown voltage Temperature dependence of avalanche breakdown voltage in p—n junctions† , 1972 .

[23]  S. M. Sze,et al.  Physics of semiconductor devices , 1969 .