Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits

As IC technology scales down, power supply voltage and temperature variations play an increasing role in signal integrity loss, which lead to performance degradation, reliability problems and functional errors. In this paper, we propose a new methodology to improve synchronous circuits' tolerance to power-supply voltage and temperature oscillations, without degrading its performance. The underlying principle of the proposed methodology is to introduce additional tolerance to the clock edge trigger in specific memory cells, by dynamically controlling the instant of occurrence of the clock edge trigger. The clock duty-cycle (CDC) is locally modulated, according to the signal propagation delay through the logic whose power supply voltage or temperature is being disturbed. The methodology is based on a clock stretching logic (CSL) block, used to dynamically modify the CDC, while maintaining at-speed clock rate. Moreover, when clock frequency reduction is inevitable, it improves circuit tolerance when the disturbances start to occur, allowing the clock generator to react and reduce its frequency. Experimental results based on SPICE simulations for two ITC99 benchmark circuits are used to demonstrate the usefulness of the proposed methodology.