A low-cost 0.98μW0.8V oversampled SAR ADC with pre-comparison and mismatch error shaping achieving 84.5dB SNDR and 103dB SFDR

Autonomous sensor nodes require ADCs with high linearity and resolution, which should operate at a low supply voltage and ensure a low absolute power consumption. Moreover, they should be low cost by minimizing chip area, using a cost-effective technology node, and being calibration free.

[1]  Xing Wang,et al.  9.3 A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2nd-Order Mismatch Error Shaping , 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

[2]  Nan Sun,et al.  9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier , 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

[3]  Michael P. Flynn,et al.  9.4 A 4th-Order Cascaded-Noise-Shaping SAR ADC with 88dB SNDR Over 100kHz Bandwidth , 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

[4]  Tien-Yu Lo,et al.  27.2 an oversampling SAR ADC with DAC mismatch error shaping achieving 105dB SFDR and 101dB SNDR over 1kHz BW in 55nm CMOS , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[5]  Arthur H. M. van Roermund,et al.  11.1 An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1dB SNDR , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).