40 MHz IF 1 MHz Bandwidth Two-Path Bandpass ΣΔ Modulator With 72 dB DR Consuming 16 mW

A bandpass modulator with two time-interleaved second-order modulators and cross-coupled paths is described. Split zeros around the 40 MHz IF provide a signal band of 1 MHz with 72 DR and 65.1 dB peak SNR. The circuit, integrated in a 0.18 CMOS technology, uses a 60 MHz clock per channel. Experimental results show that the in-band region is not affected by tones caused by mismatches and that a two-tones input causes an IMD signal of 68 . The power consumption is 16 mW with 1.8 V supply.

[1]  Howard C. Luong,et al.  A 1V 10.7MHz switched-opamp bandpass ∑Δ modulator using double- sampling finite-gain-compensation technique , 2001 .

[2]  V.S.L. Cheung,et al.  A 3.3-V 240-MS/s CMOS bandpass /spl Sigma//spl Delta/ modulator using a fast-settling double-sampling SC filter , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[3]  Saska Lindfors,et al.  A Dual-Mode 80MHz Bandpass DS-Modulator for a GSW/WCDMA IF-receiver , 2002 .

[4]  V.S.L. Cheung,et al.  A 1 V 10.7 MHz switched-opamp bandpass /spl Sigma//spl Delta/ modulator using doublesampling finite-gain-compensation technique , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[5]  Colin Lyden,et al.  A high pass switched capacitor ΣΔ modulator , 2002, ICECS.

[6]  José Silva-Martínez,et al.  A 92MHz, 80dB peak SNR SC bandpass /spl Sigma//spl Delta/ modulator based on a high GBW OTA with no Miller capacitors in 0.35/spl mu/m CMOS technology , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[7]  F. Maloberti,et al.  A mirror image free two-path bandpass /spl Sigma//spl Delta/ modulator with 72 dB SNR and 86 dB SFDR , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[8]  Rui Yu,et al.  A 47.3-MHz SAW resonator based CMOS second-order bandpass sigma-delta modulator with 54-dB peak SNDR , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[9]  J. Bjornsen,et al.  A cost-efficient high-speed 12-bit pipeline ADC in 0.18-/spl mu/m digital CMOS , 2005, IEEE Journal of Solid-State Circuits.

[10]  Franco Maloberti High-speed data converters for communication systems , 2001 .

[11]  A. Baschirotto,et al.  A 10.7-MHz self-calibrated switched-capacitor-based multibit second-order bandpass /spl Sigma//spl Delta/ modulator with on-chip switched buffer , 2004, IEEE Journal of Solid-State Circuits.

[12]  F. Kuttner,et al.  A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-/spl mu/m digital CMOS , 2005, IEEE Journal of Solid-State Circuits.

[13]  Bjørnar Hernes,et al.  A cost-efficient high-speed 12-bit pipeline ADC in 0.18-μm digital CMOS , 2005 .

[14]  P. Malcovati,et al.  Two-path band-pass Δ∑ modulator with 40-MHz IF 72-dB DR at 1-MHz bandwidth consuming 16 mW , 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.

[15]  C. Lyden,et al.  A high pass switched capacitor /spl Sigma//spl Delta/ modulator , 2002, 9th International Conference on Electronics, Circuits and Systems.

[16]  Stephen H. Lewis,et al.  A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers , 1997, IEEE J. Solid State Circuits.

[17]  Franco Maloberti Data Converters , 2007 .