Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip

Two different CMOS implementations of the Manchester carry-skip adder are analyzed using the RC timing model, which provides a unified way of analyzing both CMOS circuits and interconnect. Based on the RC timing model, the authors develop efficient polynomial algorithms to determine near-optimal (in latency) as well as optimal block sizes for the one-level manchester adder with variable carry-skip. An analysis shows that the carry-skip delay in a Manchester adder block is linearly proportional to the block size. The approach provides a general paradigm for analysis and design, applicable to different models of ripple-propagation and carry skip. >