A Wide-VDD Embedded SRAM for Dynamic Voltage Asynchronous Systems

Voltage-dependent timing skews in precharge and sensing activities cause functional failure and reduce the speed of asynchronous SRAM. Data-dependent bitline leakage current further increases the timing skews and reduces the yield of asynchronous SRAM. A dual-mode self-timed (DMST) technique is developed for asynchronous SRAM to eliminate the timing-skew-induced failures and speed overhead across various process, voltage and temperature (PVT) conditions. Measurements demonstrated that the DMST technique can be operated continuously over a wide range of supply voltages, from 39.4% to 151.5% (or 212.1%, given device durability) of the nominal supply voltage (3.3V). The fabricated macros also confirmed that the DMST technique is scalable for various bitline lengths, and offers the same area overhead as conventional sense-tracking-only replica-column schemes.

[1]  Tegze P. Haraszti.  CMOS Memory Circuits , 2000 .

[2]  S. Nagai,et al.  A 1 V operating 256-Kbit full CMOS SRAM , 1990, Digest of Technical Papers., 1990 Symposium on VLSI Circuits.

[3]  Bharadwaj Amrutur,et al.  A replica technique for wordline and sense control in low-power SRAM's , 1998, IEEE J. Solid State Circuits.

[4]  B.C. Paul,et al.  Process variation in embedded memories: failure analysis and variation aware architecture , 2005, IEEE Journal of Solid-State Circuits.

[5]  R.W. Brodersen,et al.  A dynamic voltage scaled microprocessor system , 2000, IEEE Journal of Solid-State Circuits.

[6]  Jason Liu,et al.  A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[7]  Meng-Fan Chang,et al.  Supply and substrate noise tolerance using dynamic tracking clusters in configurable memory designs , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

[8]  Chua-Chin Wang,et al.  A 4-kb Low-Power SRAM Design With Negative Word-Line Scheme , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[9]  K. Yamaguchi,et al.  A 0.9-ns-access, 700-MHz SRAM macro using a configurable organization technique with an automatic timing adjuster , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[10]  H. Morimura,et al.  A step-down boosted-wordline scheme for 1-V battery-operated fast SRAM's , 1998 .

[11]  K. Ishibashi,et al.  FA 13.1: A 1V TFT-Load SRAM Using a Two-step Word-Voltage Method , 1990 .

[12]  P.A. Beerel,et al.  High performance asynchronous design using single-track full-buffer standard cells , 2006, IEEE Journal of Solid-State Circuits.

[13]  Yee William Li,et al.  High-throughput asynchronous datapath with software-controlled voltage scaling , 2004, IEEE Journal of Solid-State Circuits.

[14]  Tadahiro Kuroda,et al.  A bitline leakage compensation scheme for low-voltage SRAMs , 2001, IEEE J. Solid State Circuits.

[15]  Akira Matsuzawa,et al.  A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[16]  Alain J. Martin,et al.  Asynchronous Techniques for System-on-Chip Design , 2006, Proceedings of the IEEE.

[17]  M. Usami,et al.  A 1.8 ns access, 550 MHz 4.5 Mb CMOS SRAM , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[18]  Chua-Chin Wang,et al.  A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches , 2004, IEEE Trans. Very Large Scale Integr. Syst..

[19]  K. Ishibashi,et al.  Universal-Vdd 0.65-2.0V 32 kB cache using voltage-adapted timing-generation scheme and a lithographical-symmetric cell , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[20]  Niraj K. Jha,et al.  Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems , 2003, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21]  Muhammad M. Khellah,et al.  A 6 GHz, 16 Kbytes L1 cache in a 100 nm dual-V/sub T/ technology using a bitline leakage reduction (BLR) technique , 2002, VLSIC 2002.

[22]  G.A. Rincon-Mora,et al.  A low voltage, dynamic, noninverting, synchronous buck-boost converter for portable applications , 2004, IEEE Transactions on Power Electronics.

[23]  Atila Alvandpour,et al.  A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme , 2003 .

[24]  Bishop Brock,et al.  A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling , 2002, IEEE J. Solid State Circuits.

[25]  H. Suzuki,et al.  A 6 ns 1.5 V 4 Mb BiCMOS SRAM , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[26]  K. Ishibashi,et al.  0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme , 2004, IEEE Journal of Solid-State Circuits.

[27]  R. I. Kung,et al.  Two-13 ns-64K CMOS SRAM's with very low active power and improved asynchronous circuit techniques , 1986 .