Improved BoothEncoding forReduced AreaMultiplier

indesigning highdensity circuit, size isa majorconcern indesign. Thispaper presents a simple modification totheBooth Multiplier thatcaneffectively reduce thearea withan accepted scarified in speed.A conventional BoothMultiplier consists of Booth Encoder, PartialProductand SummationTree.Rizalafande(i) introduced newdesign technique ingenerating thepartial product'srow. MeanwhileHsin-Lei(2) introduced a novelcircuit for Booth Encoder/Decoder whichclaims hisdesign a smaller design. Inthis propose design, weare still usingRizalafande's architecture but replace theboothencoderwithHsin-Lei encoder. Thedesign wasimplemented using theFLEXIOKEPFlOK70RC240-4 device and Altera MaxPlus+II software.