The Analysis of Phase-Jitter Variance for the Second-Order CPPLL Frequency Synthesizer
暂无分享,去创建一个
[1] Bishnu Charan Sarkar,et al. Additive Noise Response of a Charge Pump Phase-Locked Loop , 1999 .
[2] D. Leeson. A simple model of feedback oscillator noise spectrum , 1966 .
[3] Ulrich L. Rohde. Digital PLL frequency synthesizers , 1982 .
[4] F. Gardner,et al. Charge-Pump Phase-Lock Loops , 1980, IEEE Trans. Commun..
[5] A. Mehrotra,et al. Noise analysis of phase-locked loops , 2002 .
[6] Chih-Kong Ken Yang,et al. Jitter optimization based on phase-locked loop design parameters , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
[7] I. S. Gradshteyn,et al. Table of Integrals, Series, and Products , 1966 .
[8] A.A. Abidi,et al. High-frequency noise measurements on FET's with small dimensions , 1986, IEEE Transactions on Electron Devices.
[9] Beomsup Kim,et al. Optimal loop bandwidth design for low noise PLL applications , 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.
[10] A. Hajimiri,et al. Noise in phase-locked loops , 2001, 2001 Southwest Symposium on Mixed-Signal Design (Cat. No.01EX475).