Pipelined Floating Point Arithmetic Optimized for FPGA Architectures

There are many methods to perform floating point arithmetic functions. Until recently, such circuits could not be efficiently implemented in FPGAs due to their small size and low speed. The limited resources of FPGAs, both in terms of logic functions and routing seriously limits the complexity of a design that uses floating point arithmetic. We will show alternative algorithms that take advantage of the features of FPGA architecture can yield impressive performance and very small area requirements. We also describe efficient architectures for designing pipelined floating point units for addition/subtraction, multiplication and division that were used for 3D computer graphics applications in FPGAs. By exploiting the intrinsic architecture of such devices, and overcoming the limitations of VHDL and synthesis tools, these pipelined arithmetic units allow the use of multiple floating point units on the same device.