Two gates are better than one [double-gate MOSFET process]

A planar self-aligned double-gate MOSFET process has been implemented where a unique sidewall source/drain structure (S/D) permits self-aligned patterning of the back-gate layer after the S/D structure is in place. This allows coupling the silicon thickness control inherent in a planar, unpatterned layer with VLSI self-alignment techniques and also gives independently controlled front and back gates. The demanding structure led to process innovations primarily in front-end CMP, where planarity within 5 nm was achieved on an 8-in diameter wafer as well as in silicided silicon source/drain sidewalls, with minimal encroachment of the silicide. Double-gate FET (DGFET) operation is demonstrated, with good transport at both interfaces. Dense circuit layouts are achieved with multifinger devices, and logic inverters with back-gate-controlled load current as well as NOR logic using the two gates of a single transistor as inputs are demonstrated.

[1]  Albert H. Liu,et al.  Utilization of optical metrology as an in-line characterization technique for process performance improvement and yield enhancement of dielectric and metal CMP in IC manufacturing , 1999, Other Conferences.

[2]  W.C. Lee,et al.  Preparation of 200 mm silicon substrates with metal ground-plane for double-gate SOI devices , 2000, 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125).

[3]  Paul M. Solomon,et al.  Characterization of the silicon on insulator film in bonded wafers by high resolution x-ray diffraction , 1999 .

[4]  C. Hu,et al.  Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[5]  Hiroshi Iwai,et al.  Silicided silicon-sidewall source and drain (S/sup 4/D) structure for high-performance 75-nm gate length pMOSFETs , 1995, 1995 Symposium on VLSI Technology. Digest of Technical Papers.

[6]  L. Selmi,et al.  Low field mobility of ultra-thin SOI N- and P-MOSFETs: Measurements and implications on the performance of ultra-short MOSFETs , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[7]  Toshihiro Sugii,et al.  Ultrafast low-power operation of p/sup +/-n/sup +/ double-gate SOI MOSFETs , 1994, Proceedings of 1994 VLSI Technology Symposium.

[8]  T. Fukai,et al.  45-nm gate length CMOS technology and beyond using steep halo , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[9]  Roger Fletcher,et al.  A Rapidly Convergent Descent Method for Minimization , 1963, Comput. J..

[10]  S. Takagi,et al.  On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration , 1994 .

[11]  D. Hisamoto,et al.  A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET , 1989, International Technical Digest on Electron Devices Meeting.

[12]  K. Steinhubl.  Design of Ion-Implanted MOSFET'S with Very Small Physical Dimensions , 1974 .

[13]  Anna Mathai,et al.  High-resolution profilometry for improved overlay measurements of CMP-processed layers , 1998, Advanced Lithography.

[14]  D. Frank,et al.  Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[15]  M. V. Fischetti,et al.  Monte Carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go? , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[16]  Karey Holland,et al.  Endpoint detection for CMP , 1998 .

[17]  D. Frank,et al.  Generalized scale length for two-dimensional effects in MOSFETs , 1998, IEEE Electron Device Letters.

[18]  H.-S.P. Wong,et al.  Experimental evaluation of carrier transport and device design for planar symmetric/asymmetric double-gate/ground-plane CMOSFETs , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[19]  Dimitri A. Antoniadis,et al.  Back gated CMOS on SOIAS for dynamic threshold voltage control , 1995, Proceedings of International Electron Devices Meeting.

[20]  Inna V. Babich,et al.  100-nm gate lithography for double-gate transistors , 2001, SPIE Advanced Lithography.

[21]  Ronald J. Gutmann,et al.  Chemical Mechanical Planarization of Microelectronic Materials , 1997 .

[22]  Gerold W. Neudeck,et al.  New planar self-aligned double-gate fully-depleted P-MOSFETs using epitaxial lateral overgrowth (ELO) and selectively grown source/drain (S/D) , 2000, 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125).

[23]  R. Bez,et al.  A physically-based model of the effective mobility in heavily-doped n-MOSFETs , 1998 .

[24]  E. Nowak,et al.  High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[25]  G. Dewey,et al.  30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[26]  Yuan Taur,et al.  Design and performance considerations for sub-0.1 /spl mu/m double-gate SOI MOSFET'S , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[27]  Paul M. Solomon,et al.  Interface studies of tungsten gate metal–oxide–silicon capacitors , 2001 .

[28]  J. Bokor,et al.  A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation , 1994, IEEE Electron Device Letters.

[29]  M. Bruel,et al.  Smart-Cut: A New Silicon On Insulator Material Technology Based on Hydrogen Implantation and Wafer Bonding*1 , 1997 .

[30]  Qi Xiang,et al.  15 nm gate length planar CMOS transistor , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[31]  H.-S.P. Wong,et al.  Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[32]  Yuan Taur,et al.  Device scaling limits of Si MOSFETs and their application dependencies , 2001, Proc. IEEE.

[33]  Stephen Y. Chou,et al.  Wire-channel and wrap-around-gate metal–oxide–semiconductor field-effect transistors with a significant reduction of short channel effects , 1997 .

[34]  David J. Frank,et al.  Nanoscale CMOS , 1999, Proc. IEEE.

[35]  Yuan Taur,et al.  On "effective channel length" in 0.1-μm MOSFETs , 1995, IEEE Electron Device Letters.

[36]  W. Lai,et al.  The Vertical Replacement-Gate (VRG) MOSFET: a 50-nm vertical MOSFET with lithography-independent gate length , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[37]  Paul M. Solomon,et al.  A Self-Aligned Silicide Process for Thin Silicon-on-Insulator MOSFETs and Bulk MOSFETs with Shallow Junctions , 2001 .