QRS/BIST: a reliable heart rate monitor ASIC

The design of a real-time heart rate monitor implemented as a single application-specific integrated circuit (ASIC) is presented. The goal of the project was to implement a QRS detection algorithm into a single-chip environment. The testability strategies used to increase device reliability, including the implementation of built-in-self test (BIST) features, are described.<<ETX>>

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