We describe a FPGA-based, 96-channel, time-to-digital converter (TDC) intended for use with the central outer tracker (COT) in the CDF experiment at the Fermilab Tevatron. The COT system is digitized and read out by 315 TDC cards, each serving 96 wires of the chamber. The TDC, which is implemented as a 9U VME card, has been built around two Altera Stratix FPGAs. The special capabilities of this device are the availability of 840 MHZ LVDS inputs, multiple phase locked clock modules, and abundant memory. The TDC system would operate with an input resolution of 1.2 ns, a minimum input pulse width of 4.8 ns and a minimum separation of 4.8 ns between pulses. Each wire input can accept up to 7 hits per collision. Memory pipelines are included for each channel to allow deadtimeless operation in the first-level trigger; the pipeline has a depth of 5.5 /spl mu/s to allow the data to pass into one of four separate level-two buffers for readout. If the level-two buffer is accepted, the data are passed through a processor implemented in the FPGA to encode the relative time-to-digital values by using the memory positions and addresses of the transitions due to the input pulses. This processing and moving of the data takes 12 microseconds; the results are then loaded into an output VME memory. A separate memory contains the resulting word count, which is used in performing a VME 64-bit chain block transfer of an entire sixteen-card crate. The TDC must also produce prompt trigger flags for a tracking trigger processor called the extremely fast tracker (XFT). This separate path uses the same input data but passes the stream through a special processor, also implemented in the FPGA, to develop the trigger data delivered with a 22 ns clock to the XFT through a high-speed transmission cable assembly. The full TDC design and multi-card test results will be described.