Architecture Exploration of Multicore Systems-on-Chip using a TLM-based Framework

A framework for TLM architecture exploration of multi-core systems is presented. Starting with a Task Precedence Graph (TPG) as a design entry, different architectures with different number of processor cores, number of busses, task-to-processor and channel-to-bus mappings are automatically generated. The viability and potential of the proposed approach is demonstrated by an illustrative example.

[1]  Grant Martin,et al.  Overview of the MPSoC design challenge , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[2]  Frédéric Pétrot,et al.  MPSoC Communication Architecture Exploration Using an Abstraction Refinement Method , 2008, 21st International Conference on VLSI Design (VLSID 2008).

[3]  Chantal Ykman-Couvreur,et al.  MULTICUBE: Multi-objective Design Space Exploration of Multi-core Architectures , 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

[4]  Frank Ghenassia.  Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems , 2010 .

[5]  Ashraf Salem,et al.  Optimal Scheme for Search State Space and Scheduling on Multiprocessor Systems , 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..