Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes

The problem of designing a fault-secure interface between a fault-tolerant RAM memory system and a transmission channel, both protected against errors using cyclic linear error detecting and/or correcting codes is considered. The main idea relies on using the RAM check bits to control the correct operation of the parallel cyclic code encoder, so that the whole interface has no single point of failure.

[1]  Eiji Fujiwara,et al.  Error-control coding for computer systems , 1989 .

[2]  Fabrice Monteiro,et al.  Designing fault-secure parallel encoders for systematic linear error correcting codes , 2003, IEEE Trans. Reliab..

[3]  Shu Lin,et al.  Error control coding : fundamentals and applications , 1983 .

[4]  C.W. Slayman,et al.  Cache and memory error detection, correction, and reduction techniques for terrestrial servers and workstations , 2005, IEEE Transactions on Device and Materials Reliability.

[5]  Salvatore Pontarelli,et al.  A self checking Reed Solomon encoder: design and analysis , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[6]  R.C. Baumann,et al.  Radiation-induced soft errors in advanced semiconductor technologies , 2005, IEEE Transactions on Device and Materials Reliability.