Generowanie optymalnych wektorów testowych pamięci RAM

[1]  Ireneusz Mrozek,et al.  Multi Background Memory Testing , 2007, MIXDES 2007.

[2]  Kewal K. Saluja,et al.  Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Erik Jan Marinissen,et al.  Challenges in embedded memory design and test , 2005, Design, Automation and Test in Europe.

[4]  Svetlana V. Yarmolik,et al.  Address sequences for march tests to detect pattern sensitive faults , 2006, Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06).

[5]  Michael Nicolaidis,et al.  TRANSPARENT BIST FOR RAMS , 1992, Proceedings International Test Conference 1992.

[6]  Mark G. Karpovsky,et al.  Pseudo-exhaustive word-oriented DRAM testing , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[7]  A. J. van de Goor,et al.  Testing Semiconductor Memories: Theory and Practice , 1998 .

[8]  Bruce F. Cockburn.  Deterministic tests for detecting scrambled pattern-sensitive faults in RAMs , 1995, Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing.