Full-CMOS 0.13um 공정을 이용한 GPS L1-Band용 저 전력 수신기 설계

This paper presents receiver for GPS(Global Positioning System) L1-Band. The circuits are designed with Full-CMOS 0.13um technology. The receiver is based on a 4.092MHz low-IF architecture to alleviate the DC-offset problem. It includes a Low Noise Amplifier(LNA), a down conversion mixer. And the system noise figure is(NF) 3.9dB. To meet attenuation performance, the 3rd-order Chebyshev Band-Pass Filter is designed as the baseband IF filter. Capacitors and resistors arrays set the cut-off frequency and the center frequency, respetively. The Variable Gain Amplifier (VGA) is designed to have a wide dynamic range and gain control range because the level of GPS signal is very small. It designed the gain range is 0~62.5dB. Phase noise of VCO is -123dBc/Hz at 1MHz offset. To reduce current of frequency divider, dynamic Flip-Flop is used. To minimize capacitor layout area of loop filter, Active 2 rd loop filter is designed. The total power consumption is 19 mW at 1.2V supply voltage.