This paper summarizes our current effort in the BEE2 project to design and construct a high-end reconfigurable computer (HERC) system based solely on field programmable gate arrays (FPGAs) as the processing elements. FPGAs offer many important advantages over conventional microprocessors, such as flexible arithmetic precision, higher computational density per unit silicon area, and lower power consumption. The programmable interconnect structure unique to FPGA technology has made it possible to tailor a HERC system, such as the BEE2 system, on a per-problem basis to best take advantage of task specific dataflow, memory access patterns, and node-to-node communication patterns. The BEE2 project is a coordinated attack on the elements needed to demonstrate a practical, costeffective, high-end reconfigurable computer: the design of a processing module to be used as the building block for a family of high-end reconfigurable computers; the development of several programming models; and the demonstration of the efficiency of the machine on a set of applications drawn from various research projects at Berkeley Wireless Research Center (BWRC), ranging from high-performance DSP and communication systems to traditional scientific computing. Preliminary analyses show that on selected DSP applications, when compared to a microprocessor-based system with similar power consumption and cost, BEE2 can provide over 10 times more computational efficiency.
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