论文信息 - Circuit Recognition and Verification Based on Layout Information

Circuit Recognition and Verification Based on Layout Information

The mathematical and technical background information for our highly efficient procedure of circuit recognition and verification from layout information is presented. Complete verification and extremely short computing times are the main goals. This procedure can be performed for bipolar as well as for MOS technologies and is part of the whole layout-control system LOCATE.

I. Ablasser | U. Jäger

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