LFSR Reseeding Methodology for Low Power and Deterministic Pattern

An efficient low power built-in self-test methodology based on linear feedback shift register reseeding is proposed. This new method divides each test cube into several blocks and encodes that cube into a new test cube. In the new encoded test cube, the nontransitional blocks which no specified bits is included or only one kind of specified bit (1 or 0) is encoded into only one bit (1, 0, or X). The proposed method can prevent all transitions in the non-transitional blocks and can reduce the number of the specified bits for the non-transitional blocks. Experimental results for the largest ISCAS 89 benchmark circuits show that the proposed scheme can significantly reduce the power dissipation.

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