A Technique for Reducing Column-Wise FPN of CMOS Image Sensors

The generation process of the column-wise FPN in the column parallel readout circuits of CMOS image sensors is discussed when CDS circuits suppreses KTC noise, 1/f noise, and FPN from the pixel. In order to remove the column-wise FPN, an instrument structure readout circuit with accurate balancing differential output is provided, which can be used to compensate the column processing circuits offset variation combined with CDS technique.